
Marco Bertuletti
@marcobertuletti
Italian based in Zürich, hardware engineer
ID: 1570137456598519809
14-09-2022 19:48:59
28 Tweet
53 Followers
58 Following

Our Gianna Paulin is presenting Occamy at #DATE2023 and Bianca The Bear is paying attention. Occamy is our super ambitious project. The compute die contains 216 RISC-V cores and includes an HBM controller. asic.ethz.ch/2022/Occamy.ht…


I will join, of course! Yichao, Zhang and me will present on the TeraPool project: 1000s cores for B5G and 6G processing!

On the stage! The PULP Platform anniversary in Lugano was great. I’m glad I had the opportunity to meet the whole team and present my research with Yichao, Zhang.

The poster session is under way at #RISCVSummitEurope in Barcelona and here we have Marco Bertuletti explaining his work on "Parallel Sparse Deep Learning Operators on Lightweight RISC-V Processors" riscv-europe.org/media/proceedi…


Upon popular request, we released an early version of our new Network-on-Chip FlooNoC on Github github.com/pulp-platform/…. Make sure you state your destination clearly, otherwise your packets might end up somewhere else 🔮🧙🍵. Tim Fischer



Our paper "Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster" focusing on barrier synchronization for TeraPool is now on arXiv. Check it out: arxiv.org/pdf/2307.10248… Marco Bertuletti Samuel Yichao, Zhang Alessandro Vanelli-Coralli




Congrats for the amazing work to Yichao, Zhang!

After Maestro and Heartstream, with GF22 “Buckbeak” I celebrate the third successful tape-out project in six months… only in PULP Platform! The Spatz cluster I mainly worked on is right below the hippogriff 🐎🦅, and it contains a configurable dual-core vector processor.

Our "TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios" by Yichao, Zhang landed with Marco Bertuletti in Tampa FL where it was presented at #GLSVLSI2024. Learn more dl.acm.org/doi/10.1145/36… & pulp-platform.org/docs/glsvlsi20…


Our Yichao Yichao, Zhang is currently in Tanger 🇲🇦 attending VLSI-SoC. You can find his poster & paper on TeraPool "1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR" here: pulp-platform.org/docs/vlsisoc20… pulp-platform.org/docs/vlsisoc20… Marco Bertuletti Samuel


Wonderful news from Tangier! Our paper on TeraPool "A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR" just won the Best PhD forum Award at VLSI-SoC 2024. Below Yichao Yichao, Zhang with Henk Corporaal 🇳🇱 & Said Hamdioui receiving the award🏆.


Our 64-core RISC-V chip Heartstream just came back from the fab. Thank you GlobalFoundries UPP for supporting us with this project. Learn more about the chip in our ASIC gallery: asic.ethz.ch/2024/Heartstre…. Time to test🥼🐻!


#DAC2025 is about to start and we are ready! Marco Marco Bertuletti and Luca Luca Colagrande made it to from the bottom of the Yosemite Valley to the Clouds Rest (1940m elevation gain). And they promised to wash their PULP T-shirts before the conference😀 .


Meet us at #DAC2025 for "Fast End-to-End Simulation and Exploration of Many-Core Baseband Transceivers for Software-Defined Radio-Access Networks" presented by Marco Marco Bertuletti on Monday, June 23 in Room: 3008, Level 3, at 3:30 pm: 62dac.conference-program.com/presentation/?…


#DAC2025 is underway! You can now find Marco's Marco Bertuletti poster and slides presenting "Fast End-to-End Simulation and Exploration of Many-RISCV-Core Baseband Transceivers for SDR-Access Networks" on our website: pulp-platform.org/docs/dac2025/M… and pulp-platform.org/docs/dac2025/M…


The "Birds of Feather" meeting on open source EDAs took place at #DAC2025 yesterday. Here are the photos and slides from Marco's Marco Bertuletti talk "Open-Source From Ideas to Silicon: PULP Teaching & Research with Open IPs, EDAs, PDKs" pulp-platform.org/docs/dac2025/M…
