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TFW you when you realise something you want obviously exists, you didn't think about it the right way. #riscv me: it would be cool if there was an instruction that swapped 1 and -1 in a register riscv: there's a pseudoinstruction for that! **neg** me: oh yeah

Good news open-source #FPGA fans, there's a new release of nextpnr (place and route) from YosysHQ. The release notes mention "Numerous improvements to Gowin support": github.com/YosysHQ/nextpn…

"It invariably delivered a cupful of liquid that was almost, but not quite, entirely unlike tea." 🫖

What do we know about the Gowin GW5A #FPGA (GW5AT-LV60P484A) found on the Tang Console? Board pricing looks reasonable, but I'm naturally concerned about open-source support. I did see some discussion at Project Apicula last year: github.com/YosysHQ/apicula

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Vibe Coding “Raw and Unedited”. This appears to be a real book from O’Reilly. 🤔 oreilly.com/library/view/v…

My Earthrise #FPGA drawing engine rendering vector letters on #ULX3S dev board connected to 1024x768 LCD panel via Pimoroni controller board (handles HDMI to FPD-Link LVDS). 🌍

Working on an #FPGA demo for NOVA demoparty in June. Verilator/SDL simulation for quick turnaround when designing vector graphics. I think this year's wild compo will be epic.

I'm not a great FGPA programmer, but I just took a crack at a 10 PRINT in Verilog. It took me a while to achieve the typewriter effect that resembles the one on an 8-bit machine. I'm happy with the way it turned out. Big thanks to Flux for the tutorials on FPGA graphics.

I'm considering #RISCV CPUs. I'm looking for open source RV32IMC with good debugging support and interrupts. Simplicity is more important than performance. I prefer Verilog. VexRiscv is an old favourite and Hazard3 is an interesting new option. What else should I consider? #FPGA