Grateful to PULP Platform for engaging across the RISC-V International community! Perhaps we need a Zurich reunion workshop to get the band fully assembled

The PULP team is in Paris rocking the #RISCV week🎸. We hope this picture is sufficient as our WR (weekly report) Luca Benini @alaasalman31

Super excited of having joined #Spring2022RISCVWeek with my poster. RISC-V International has an amazing and energetic community, proud to be part of it! PULP Platform

#RISC-V week in Paris has been a truly great event! To conclude it in style Alaa @alaasalman31 , Sergio Sergio Mazzola, and Alessandro Alessandro Ottaviano brought one of PULP posters into the French skies 🗼🪂🌤️. See you all at another great RISC-V event!

We're presenting at Samos Conference today👇 ⏰8.30h CEST "A Data-Driven Approach to Lightweight DVFS-aware Counter-based Power Modeling for Heterogeneous Platforms" by Sergio Mazzola PULP Platform #EmbeddedHPC ampere-euproject.eu/events/samos-c…

SAMOS XXII is under way and Sergio Sergio Mazzola shared with us a couple of moments. We give you Robert presenting ControlPULP, Yale Patt talking about the future microprocessors and a boat trip to an islet of Samiopoula. samos-conference.com/wp/

Thank you HiPEAC for organizing the ACACES Summer School 2022. We had a wonderful time. See you all next year! Luca Valente Sergio Mazzola Francesco Conti 🇮🇹🇪🇺 Luca Colagrande Nils Wistoff

And now something for fans of modern counter-based power models. Here are the slides from Sergio's Sergio Mazzola talk at Samos XXII "A Data-Driven Approach to Lightweight DVFS-Aware Counter-Based Power Modeling for Heterogeneous Platforms". AMPERE pulp-platform.org//docs/samos202…

Time for 🌊"Diving into MemPool: Scaling the Shared-Memory Cluster to 256 Cores" with Samuel Samuel at PULP get-together in Lugano 😀. Check out the slides from his talk: pulp-platform.org/docs/lugano202…

Just in time for Valentine’s Day, here comes the first PULP chip of the year: Heartstream in GF12. An implementation of our MemPool architecture with 64 RISC-V cores. Supported by GlobalFoundries UPP asic.ethz.ch/2024/Heartstre…

Our new paper aiming at efficient systolic execution on shared L1-memory manycore clusters is now on arXiv. Demonstrated on MemPool, check out "Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters" Sergio Mazzola Samuel arxiv.org/pdf/2402.12986…

Are you ready for the EFCL Summer School? We are! The big shopping for the next week just arrived and our guys Sergio Mazzola, Luca Bertaccini, Thomas Benz and Alessandro Ottaviano are working hard to give you a great experience 😋🍷☕️. See you soon at efcl.ethz.ch/efcl-summer-sc….

Here we come with Heartstream and Charlie The Bear in full beauty: How to tape-out a 64-core RISC-V SoC in under 60 days pulp-platform.org/docs/riscvmuni… Paper: pulp-platform.org/docs/riscvmuni… Sergio Mazzola Yichao, Zhang Samuel Marco Bertuletti just presented at #RISCV Summit in Munich.

More from Charlie The Bear at the #RISCV Summit EU in Paris 😀. Below our guys Victor Victor Jung , Sergio Sergio Mazzola who together with Charlie The Bear welcome the new #RISCV CEO Andrea Gallo.

Sergio's Sergio Mazzola #RISCV Summit EU presentation on "MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster" is now online, as well: pulp-platform.org/docs/riscvsumm…

And here is the video " MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster" youtube.com/watch?v=MvZnyX… presented by Sergio Sergio Mazzola at the #RISCV Summit Europe. You can find the slides here: pulp-platform.org/docs/riscvsumm…